This invention relates to correcting design data for manufacture.
A conventional integrated circuit design process includes two major operations: logic design and physical design. During the logic design, a design concept is ordinarily described using a hardware description language and is then converted into netlist data, i.e. circuit design data in a schematic form, specifying electronic components at a functional level and the connections between these components. During the physical design, the manner in which circuit components and connections are to be placed and routed is determined. Once placement of the components and routing of the connections are determined, physical design data, i.e. circuit design data in a form that can be used in the fabrication of the circuit on wafer, is generated for controlling integrated circuit (IC) fabrication. The physical design data defines a set of binary patterns. The physical design data generally defines each pattern as multiple polygons (usually rectangles), which are frequently referred to as geometric features. Each polygon has edges, and each edge is defined by integer value coordinates of its two opposite ends in an x, y coordinate system. The polygons may include rectangles each having a long edge aligned with one of the coordinate axes and a short edge aligned with the other coordinate axis.
An optical lithographic stepper system or other patterning system transfers the patterns defined by the physical design data sequentially to a semiconductor wafer. Each pattern, as thus transferred, specifies areas of the wafer that are to be processed in a subsequent manufacturing step. The lithographic system maps the coordinate system in which the edges of the polygons are defined with reference to a predefined square array of grid points with a certain step size. For example some designs use a 10 nm step size (wafer level).
Generation of the physical design data is typically iterative, in that the software tool that is used to generate the physical design data from the netlist data iteratively modifies the layout or pattern until it arrives at a layout that satisfies a set of constraints called the manufacturing design rules. These constraints include within layer physical design constraints and the inter-layer physical design constraints derived from lithographic and device manufacturing capabilities.
The result of transferring a geometric feature to the wafer is referred to as the wafer result. The wafer result does not necessarily match precisely the corresponding geometric feature. For example, the patterning system may introduce distortion into the transfer of the features of the physical design data to the wafer, and the manufacturing processes, including, e.g. manufacture of lithographic exposure masks and chemical processing of the wafer, may result in further deviation between a feature of the physical design data and the physical embodiment of that feature in the processed wafer. A geometric feature may have associated tolerances, which specify variations permitted in the wafer result of a geometric feature such that even though the manufactured circuit does not match precisely the physical design data, the manufactured circuit will nevertheless meet the circuit performance specification. For a given geometric feature, tolerances may include specification of boundaries for the location of an edge of a rectangle along a direction perpendicular to the length of that edge in addition to the permitted variation in its critical dimension(s) on wafer. The critical dimension is the length measurement of the geometric feature that is critical. For example for a gate layer, the device gate length is a critical dimension, while for the landing pad, the two dimensions of length and width are critical dimensions.
The definition of physical design data does not preclude the possibility of corrections or adjustments. The technique known as optical and process correction (OPC) is an approach to making corrections to the physical design data in order to accommodate differences between the image transferred to the wafer and the intended design due to distortion introduced by the patterning system and the manufacturing processes. OPC thus alters the original physical layout (defined by the physical design data) to compensate for distortions caused by, for example, local optical diffraction, long range effects such as etch loading on mask and wafer, optical flare, and resist process effects among others. So-called model based OPC may be performed by modeling the final manufactured output of a semiconductor design and then determining what changes should be made to the physical design data to obtain a desired end result. Rule based OPC involves creating and applying a set of correction rules. Each rule tests the physical design data for a particular condition where correction may be necessary and if the condition is found, applies a correction to the physical design data.
Current methods of OPC may be divided into the following different categories:                (a) Apply OPC to all features of the layout design with the same tolerance or with different tolerances depending on the geometrical shape, such as whether the feature is a straight line segment, a corner feature or a line end.        
(b) Apply OPC in a hybrid fashion of both rule-based OPC and model-based OPC.
(c) Apply OPC with different tolerances for critical and non-critical features (design aware or frugal OPC).
A disadvantage of current OPC techniques is that features are corrected without prioritization of the features as a function of the tolerance of the feature. As a result, features with smaller tolerance may be corrected before the environment of neighboring features has been fully defined and as a result there is an opportunity for error in the corrected design.